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low skew, 1-4 differential-to- lvds fanout buffer ics854104 idt ? / ics ? 1-to-4 lvds fanout buffer 1 ICS854104AG rev. a january 3, 2007 preliminary g eneral d escription the ics854104 is a low skew, high performance 1-to-4 differential-to-lvds clock fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. util- izing low voltage differential signaling (lvds), the ics854104 provides a low power, low noise, solution for dis- tributing clock signals over controlled impedances of 100 ? . the ics854104 accepts a differential input level and trans- lates it to lvds output levels. guaranteed output and part-to-part skew characteristics make the ics854104 ideal for those applications demanding well defined performance and repeatability. f eatures ? four lvds outputs ? one differential clock input pair ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? each output has an individual oe control ? maximum output frequency: 700mhz ? translates differential input signals to lvds levels ? additive phase jitter, rms: 0.1ps (typical) ? output skew: tbd ? part-to-part skew: tbd ? propagation delay: 1.1ns (typical) ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request ? available in both standard (rohs 5) and lead-free (rohs 6) packages b lock d iagram p in a ssignment hiperclocks? ic s oe0 oe1 oe2 v dd gnd clk nclk oe3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 q0 nq0 q1 nq1 q2 nq2 q3 nq3 ics854104 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view q0 nq0 q1 nq1 q2 nq2 q3 nq3 clk oe2 oe3 oe1 oe0 nclk pulldown pullup/pulldown pullup pullup pullup pullup the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? 1-to-4 lvds fanout buffer 2 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary t able 2. p in c haracteristics t able 1. p in d escriptions l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? r e b m u ne m a ne p y tn o i t p i r c s e d 10 e ot u p n ip u l l u p l l i w s t u p t u o , w o l s i n i p e o f i . t u p t u o 0 q n , 0 q r o f n i p e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . z i h e v i r d 21 e ot u p n ip u l l u p s t u p t u o , w o l s i n i p e o f i . s t u p t u o 1 q n , 1 q r o f n i p e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . z i h e v i r d l l i w 32 e ot u p n ip u l l u p s t u p t u o , w o l s i n i p e o f i . s t u p t u o 2 q n , 2 q r o f n i p e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . z i h e v i r d l l i w 4v d d r e w o p. n i p y l p p u s e v i t i s o p 5d n gr e w o p. d n u o r g y l p p u s r e w o p 6k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 83 e ot u p n ip u l l u p s t u p t u o , w o l s i n i p e o f i . s t u p t u o 3 q n , 3 q r o f n i p e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . z i h e v i r d l l i w 0 1 , 93 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 2 1 , 1 12 q , 2 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 4 1 , 3 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 6 1 , 5 10 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 3. oe[3:0] f unction t able s t u p n is t u p t u o ] 0 : 3 [ e o3 q n / 3 q : 0 q n / 0 q 0) t l u a f e d ( z i h 1e v i t c a
idt ? / ics ? 1-to-4 lvds fanout buffer 3 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, t a = 0c to 70c t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n iv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n iv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a 0 5 h t i w d e t a n i m r e t s t u p t u o : e t o n ? v o t d d . " t i u c r i c t s e t d a o l t u p t u o " , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 6a m a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o contin uous current 10ma surge current 15ma package thermal impedance, ja 89c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4c. d ifferential dc c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i , k l c k l c n v d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n , v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t d d . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i .
idt ? / ics ? 1-to-4 lvds fanout buffer 4 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary t able 5. ac c haracteristics , v dd = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p 1 . 1s n t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r ) z h m 0 2 o t z h k 2 1 (1 . 0s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o d b ts p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p d b ts p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 4s p c d oe l c y c y t u d t u p t u o 0 5% t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u : 1 e t o nv e h t m o r f d e r u s a e m d d . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t u p n i e h t f o 2 / : 2 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d v t a d e r u s a e m d d . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t u p n i e h t f o 2 / s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n t able 4c. lvds dc c haracteristics , v dd = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 0 5 3v m ? v d o v d o e g n a h c e d u t i n g a m 0 3v m v s o e g a t l o v t e s f f o 3 . 1v ? v s o v s o e g n a h c e d u t i n g a m 0 2v m
idt ? / ics ? 1-to-4 lvds fanout buffer 5 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary p arameter m easurement i nformation d ifferential o utput l evel 3.3v o utput l oad ac t est c ircuit scope qx nqx lvds 3.3v5% power supply +? float gnd 3.3v p art - to -p art s kew p ropagation d elay o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v od t sk(o) qx qy o utput s kew t sk(pp) part 1 part 2 clk t pd nqx nqy qx qy nqx nqy q0:q3 nq0:nq3 v os cross points v od gnd q0:q3 nq0:nq3 v dd nclk
idt ? / ics ? 1-to-4 lvds fanout buffer 6 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary o ffset v oltage out out lv d s dc input ? ? ? v os / v os v dd d ifferential o utput v oltage ? ? ? 100 out out lvds dc input v od / v od v dd o utput d uty c ycle /p ulse w idth /p eriod t pw t period t pw t period odc = x 100% q0:q3 nq0:nq3
idt ? / ics ? 1-to-4 lvds fanout buffer 7 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary a pplication i nformation i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. w iring the d ifferential i nput to a ccept s ingle e nded l evels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
idt ? / ics ? 1-to-4 lvds fanout buffer 8 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary 3.3v lvds d river t ermination a general lvds interface is shown in figure 2. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver f igure 2. t ypical lvds d river t ermination input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 100 ohm differiential transmission line r1 100 3.3v + - lvds_driv er 3.3v 100 ? ? ? ? ? differential transmission line
idt ? / ics ? 1-to-4 lvds fanout buffer 9 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary r eliability i nformation t ransistor c ount the transistor count for ics854104 is: 286 pin compatible with sn65lvds104 t able 6. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? 1-to-4 lvds fanout buffer 10 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary p ackage o utline - g s uffix for 16 l ead tssop t able 7. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? 1-to-4 lvds fanout buffer 11 ICS854104AG rev. a january 3, 2007 ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 4 0 1 4 5 8 s c ig a 4 0 1 4 5 8p o s s t d a e l 6 1e b u tc 0 7 o t c 0 t g a 4 0 1 4 5 8 s c ig a 4 0 1 4 5 8p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l g a 4 0 1 4 5 8 s c id b tp o s s t d a e l 6 1e b u tc 0 7 o t c 0 t f l g a 4 0 1 4 5 8 s c id b tp o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics854104 low skew, 1-to-4 differential-t o-lvds fanout buffer preliminary

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